It appears that sedeleg and sideleg were also defined by the now-defunct "N" extension, so please remove those, too.

That leaves sie (defined by "S" extension), dscratch0 and dscratch1 (defined by "Sdext" extension).

Looks like to get these new CSRs to pass the CI tests, we'll need to add the fields.

• For sie, that points to scause for interrupt values. scause is defined in UDB and has some code that seems to beg for expansion, but I don't see anything that performs that expansion. If you want to replicate the incomplete implementation in scause into sie, that's fine for now, just to get the basics of sie defined in UDB.
• dscratch0 and dscratch are generic registers which just contain a "value", so let's define a field, "VALUE" of MXLEN bits. See "mtval.yaml" for an example.

[FYI, I removed "ustatus, uie, utvec, uscratch, uepc, ucause, utval, uip, sedeleg, sideleg" from the PR description.]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 46.05%. Comparing base (15e139b) to head (132d6c8).
⚠️ Report is 3 commits behind head on main.

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  Coverage   46.05%   46.05%           
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  Files          11       11           
  Lines        4942     4942           
  Branches     1345     1345           
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  Hits         2276     2276           
  Misses       2666     2666           

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